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Open Source Chip Design

October 27 @ 6:30 pm 8:30 pm EDT

Attendance: 109 / 200, Remaining: 91

Registrations are closed for this event.

On Thursday, October 27, 2022, the IEEE Consultants’ Network of Northern New Jersey will host a presentation on Open Source Chip Design with Dr Mehdi Saligane on Zoom.

About the Topic

Lowering the barriers to chip design using OpenFASOC: Fully Autonomous System-on-Chip (FASoC) tool is a DARPA-funded project within the IDEA program. Its main objective is to address the need for analog compilers. The framework relies on the place and route digital flow which has long been extensively automated while most analog flows are still extremely reliant on manual design. This lack of analog automation tools leads to long design cycles and costs. FASoC addresses this need and uses a cell-based analog design generation methodology to generate different analog and mixed-signal (AMS) blocks (i.e., PLL, LDO, DC-DC converters, Temperature Sensors, etc.).

A few SoCs have been taped out in the SkyWater 130 nm, BI-CMOS 130 nm, TSMC 65 nm and Globalfoundries 12 nm foundry process nodes. OpenFASOC has been built on top of OpenROAD for push-button layout generation as part of the current open source effort. This talk will go through a few of our open-source analog generators (Temperature Sensor, Switched-Cap DC-DC Converter, etc.), our implemented designs in Google’s free shuttles MPW-I / II and our GF12LP tapeout of the OpenTitan SoC which heavily used open source tooling.

About the Speaker

Mehdi Saligane is a Research Scientist in the Department of Electrical Engineering and Computer Science at the University of Michigan. He received his Masters, and Ph.D. degrees in electrical and computer engineering from the University of Grenoble and Aix-Marseille in 2011 and 2016, respectively. He worked at STMicroelectronics, in France, as a Research Engineer from 2010 to 2015, and after completing his Ph.D., he joined the Michigan Integrated Circuits Lab at the University of Michigan. Dr. Saligane’s current research interests are in low-power and energy-efficient IC design with a recent focus on open-source EDA and analog and mixed-signal IC design automation. He currently serves as chair of the Analog Working Group and, as a member of the Technical Steering Committee at CHIPS Alliance, and as a technical member of SSCS’ open source ecosystem.

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